The present invention relates to a Bi-MOS logic circuit consisting of bipolar transistors and MOS FETs which are integratedly formed on the same substrate and, more particularly, to a Bi-MOS logic circuit which is used as a semiconductor logic circuit for operating a circuit having a large output load, such as an LSI memory.
The characteristic feature of a Bi-MOS logic circuit is that it has a totem pole type output buffer section which consists of two NPN bipolar transistors and is switch-controlled by a MOS circuit.
FIG. 1 shows an example of a Bi-MOS logic circuit in which the MOS circuit has a CMOS structure. This logic circuit is a well-known Bi-CMOS buffer circuit which generates an output signal having the same phase as the input signal.
The totem pole type output buffer section of this logic circuit includes pull-up NPN bipolar transistor Q5 and pull-down Schottky type NPN bipolar transistor Q6, as well as Schottky NPN bipolar transistor Q7 which is darlington-connected to transistor Q5 in order to allow the level of an output signal supplied by output terminal T2 to rise quickly.
Schottky diodes D1 and D2, on the other hand, are provided to enable the level of an output signal from terminal T2 to fall quickly.
When the input signal supplied to input terminal T1 changes from the "0" level to the "1" level, P-type MOS FET Q1 is turned off and N-type MOS FET Q2 is turned on. Thus, the potential which is supplied to a gate of N-type MOS FET Q3 is set to the "0" level and FET Q3 is turned off. As a result, the base current is supplied from power source potential Vcc to transistor Q7 via resistor R1, and transistor Q7 is turned on, as is also pull-up transistor Q5. On the other hand, no base current is supplied to pull-down transistor Q6, with the result that it is turned off. Thus, a current flows from power source potential Vcc to output terminal T2 via resistor R4 and transistor Q5, thereby setting the potential of output terminal T2 from the "0" level to the "1" level. Since transistor Q7 is darlington connected to pull-up transistor Q5, the potential change at terminal T2 occurs at a higher speed than that in the case where transistor Q7 is not used.
When the input signal level changes from "1" to "0", FET Q1 is turned on and FET Q2 is turned off, so that the potential which is supplied to the gate of FET Q3 is set to the "1" level and FET Q3 is turned on. As a result, current is supplied from power source potential Vcc to the base of pull-down transistor Q6 via resistor R1 and FET Q3. Current is also supplied from the base of transistor Q5 to the base of transistor Q6, via Schottky diode D1 and FET Q3, and is also supplied to the base of transistor Q6 from output terminal T2, via diode D2 and FET Q3. Thus, transistor Q6 is turned on. Since, at this time, no current is supplied to pull-up transistor Q5, transistor Q5 remains in the OFF state, with the result that the potential of output terminal T2, i.e., the output voltage level, changes from "1" to "0". Since the base current which is supplied to pull-down transistor Q6 is increased by the current supplied via Schottky diodes D1 and D2, the potential change at terminal T2 occurs at a higher speed than in the case where no current flows through diodes D1 and D2.
Waveform shaping circuit section 11 comprising resistors R2 and R3 and Schottky type NPN bipolar transistors Q4 is used to make constant a collector current of pull-down transistor Q6 by transistor Q4 which operates as a diode and to shape the waveform which trails from the "1" level to the "0" level.
However, when a Bi-CMOS buffer circuit is constituted as above, the following parasitic capacitances (C1, C2, C3, C4, C5) are added to the base of transistor Q7: namely, the parasitic capacitance (C1) between the drain of FET Q3 and the substrate; the parasitic capacitances (C2 and C3) between the collector and the base of transistor Q7 and between the base and the emitter thereof; and the parasitic capacitances (C4 and C5) formed between cathode of diodes D1 or D2 and the substrate.
When FET Q3 is turned off, a delay is caused in the potential increase at the base of transistor Q7 by a time constant which is determined by resistor R1 and parasitic capacitances C1 to C5. Consequently, the leading propagation delay time (t.sub.PLH) until an output signal rises to a predetermined level after the input signal supplied has reached a predetermined level is prolonged because of the parasitic capacitances C.sub.4 and C.sub.5.